Network-on- Chip Test Architectures

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Chapter p 5 System/Network--on System/Network on-Chip Test Architectures Jin-Fu Li Advanced Reliable Systems (ARES) Lab Department of Electrical Engineering National Central University Jhongli, Taiwan

Outline † † † † †

Introduction SoC Test Challenge SoC Test Access Mechanisms S C Test SoC T t Control C t lA Architectures hit t NoC Testing

Advanced Reliable Systems (ARES) Lab.

Jin-Fu Li, EE, NCU

2

What is an SOC? † Definition „ Integration of multiple cores (e.g., microprocessor, digital signal processor, RAM, ROM, flash memory, I/Os, and analog components which make a complete system) onto a single chip ADC

FPGA Flash Memory

CPU

UDL

DSP

DRAM MPEG

Advanced Reliable Systems (ARES) Lab.

SRAM

SRAM

Jin-Fu Li, EE, NCU

3

What are Cores? † Definition „ Predefined, pre-verified complex functional blocks, also k known as IPs, IP virtual i l components

† Examples „ „ „ „ „

Processor Cores: P C ARM, ARM MIPS MIPS, IBM PowerPC P PC Peripherals: MMU, DMA Controller Interface: PCI, PCI USB, USB UART Multimedia: JPEG compression, MPEG decoder Networking: Ethernet Controller, MAC

† Various core description levels „ Soft cores: register-transfer level (synthesizable HDL) „ Firm cores: gate-level netlist (Verilog netlist) „ Hard cores: layout (GDS2) Advanced Reliable Systems (ARES) Lab.

Jin-Fu Li, EE, NCU

4

Traditional & Core-Based IC Design †Traditional IC design „ IC is designed g from scratch „ Reuse of small modules: standard-cell library and memory modules

†Core-based IC design „ Reuse of large modules: cores, IP, virtual components „ Divide-and-conquer q design g methodology gy „ Definition of standards to make reuse easy „ Reduce time-to-market

Advanced Reliable Systems (ARES) Lab.

Jin-Fu Li, EE, NCU

5

Difference Between SOB and SOC System-on-Board (SOB)

System-on-Chip (SOC)

IC Design g

Core Design

IC Verification

Core Verification z

IC M Manufacturing f t i

Reuse of predeisgned components in a system

IC Test z

SOB Design g

SOC Design

SOB Verification

SOC Verification

SO Manufacturing SOB f

SOC M Manufacturing f t i

SOB Test

SOC Test

Advanced Reliable Systems (ARES) Lab.

Analogy

Jin-Fu Li, EE, NCU

Difference Cores in SOC are fabricated and tested in the final system

[Zorian, et al.-ITC97]

6

What are The Test Challenges? † Distributed design and test development „ Mixed technologies: g logic, g p processor, memory, y analog † Need various ATPG/DFT/BIST/other techniques

„ Multiple hardware description levels for cores † Need test plan for the various levels

„ Diff Differentt core providers id and d SOC test t t developers † Need standard for test integration

† Deeply embedded cores „ Need electronic test access mechanism

† Core/test reuse „ Need N d plug-and-play l d l ttestt mechanism h i Advanced Reliable Systems (ARES) Lab.

Jin-Fu Li, EE, NCU

7

What are The Test Challenges? † Hierarchical core reuse „ Need hierarchical test management

† SOC-level test optimization „ Test time can be extremely large † Need parallel testing or test scheduling

„ Test power must be considered † Need N d llow-power design d i or test t t scheduling h d li

„ Testable design automation † Need new testable design tools and flow

„ Test economic consideration † Need eed to determine dete e test strategy st ategy and a d overall o e a test plan pa

† SOC yield improvement „ Large amount of defect defect-sensitive sensitive memory cores † Need cost-effective repair techinques

Advanced Reliable Systems (ARES) Lab.

Jin-Fu Li, EE, NCU

8

Generic Test Access Structure

ADC

FPGA Wrapper

CPU

UDL

Flash Memory

DSP Sink

Source

TAM

Test Access Mechanism (TAM)

MPEG

SRAM

SRAM

DRAM

[Y. Zorian, et al.-ITC98]

Advanced Reliable Systems (ARES) Lab.

Jin-Fu Li, EE, NCU

9

1500 Test Scalable Structure Source

User Defined Parallel TAM TAM--in TAM

TAM--out TAM

TAM--in TAM

1500 Wrapper Fin

WSI

TAM--out TAM

1500 Wrapper Fout

Core1 WIR

Sink

WSO

Fin

WSI

CoreN WIR

Fout

WSO

WSC User Defined User-Defined Test Controller

Advanced Reliable Systems (ARES) Lab.

Jin-Fu Li, EE, NCU

10

1500 Parallel TAM Configuration Daisychained TAM

WPC WPI

WPO

ENA

WSI

ENA

WPP

WPP

ENA

WPP

Core

Core

Core

Wrapper

Wrapper

Wrapper

WSP

WSP

WSP

WSO

WSC Standardized Plug & Play Wrapper Serial Ports Advanced Reliable Systems (ARES) Lab.

Jin-Fu Li, EE, NCU

11

1500 Parallel TAM Configuration Bussed TAM

WPC WPI

WPO

ENA

WSI

WPP

ENA

WPP

ENA

WPP

Core

Core

Core

Wrapper

Wrapper

Wrapper

WSP

WSP

WSP

WSO

WSC

Advanced Reliable Systems (ARES) Lab.

Jin-Fu Li, EE, NCU

12

P1500 Parallel TAM Configuration Direct Access TAM

WPC WPI WPO WPC WPI ENA

WSI

WPO WPO WPC WPI

WPP

ENA

WPP

ENA

WPP

Core

Core

Core

Wrapper

Wrapper

Wrapper

WSP

WSP

WSP

WSO

WSC Advanced Reliable Systems (ARES) Lab.

Jin-Fu Li, EE, NCU

13

TAM Implementations † Many TAM implementation have been reported † Examples: p „ „ „ „ „

Multiplexed access Reused system bus (AMBA) Transparency Boundary Scan Scalable TAMs (Test bus, TestRail)

† On one SOC, different TAMs may co-exist

Advanced Reliable Systems (ARES) Lab.

Jin-Fu Li, EE, NCU

14

Multiplexed Access

[E. J. Marinissen, ITC98]

† (a): Multiplexing architecture; (b) daisy-chain architecture; (c) Distributed architecture

Core A

N

Core A na

Core B

Core B

N

Core C IC

Core C IC

(a) Advanced Reliable Systems (ARES) Lab.

nb nc

Core A Core B Core C

IC (b) Jin-Fu Li, EE, NCU

( ) (c) 15

Test Shell/TestRail

[E. J. Marinissen, ITC98]

† Every core is wrapped with a TestShell † The TestShell is the test data transport mechanism † TCM is a standardized test control mechanism in the h TestShell Sh ll † The host is the environment in which the core is embedded host

TestShell

TCM

TestRail

Advanced Reliable Systems (ARES) Lab.

TestShell

TCM

TCM

IP A

IP B

Jin-Fu Li, EE, NCU

16

Test Shell/TestRail

[E. J. Marinissen, ITC98]

host Shell

TCM

TCM 16

TestRail 1

16

16

16

Core A

Shell

Shell

TCM

TCM

Core B

Core C

16

16

16

Shell

TCM Shell

TestRail 2

10

Advanced Reliable Systems (ARES) Lab.

2

Core E

Shell

TCM

TCM

Core D

Core F

8

Jin-Fu Li, EE, NCU

10

17

Fixed-Width Test Bus Architecture B

A

C

D

E

F

SOC Advanced Reliable Systems (ARES) Lab.

Jin-Fu Li, EE, NCU

18

Fixed-Width TestRail Architecture

B

A

C

D

E

F

SOC Advanced Reliable Systems (ARES) Lab.

Jin-Fu Li, EE, NCU

19

Flexible-Width Test Bus Architecture

B

A

C

D

E

F SOC

Advanced Reliable Systems (ARES) Lab.

Jin-Fu Li, EE, NCU

20

Hierarchical Test Methodology TDI_UP

TMS_UP

TRST_UP

TCK_UP

[J.-F. Li, et al., IEEE Micro 02]

TDO_UP

HTM1 TDI_C

ECS TDI_H TCS_DN

TDO_H

TDO_C

HTM2 WCI

TAP

WCI

MBI Core 1 (P1500)

Core 2

WCI

WCI

Core 3 (P1500)

Core 4 (P1500)

(BISTed RAM)

Core 5 (JTAG)

TAM 2

TAM 1 TAM input Advanced Reliable Systems (ARES) Lab.

TAM output Jin-Fu Li, EE, NCU

21

Hierarchical Test Procedure

[J.-F. Li, et al., IEEE Micro 02]

† Test Configuration „ Load the instructions for the wrappers pp and memory BIST interfaces (MBIs)

† TAM Specification p „ Specify the cores to be tested by the TAM

† Test Transportation „ Import the test patterns and export the test responses

Advanced Reliable Systems (ARES) Lab.

Jin-Fu Li, EE, NCU

22

An Example TDI_UP

TMS_UP

TRST_UP

TCK_UP

TDO_UP

HTM1 TDI_C

ECS TDI_H TCS_DN

TDO_H

TDO_C

HTM2 WCI

TAP

WCI

MBI Core 1 (1500)

Core 2

WCI

WCI

Core 3 (1500)

Core 4 (1500)

(BISTed RAM)

Core 5 (JTAG)

TAM 2

TAM 1 TAM input Advanced Reliable Systems (ARES) Lab.

TAM output Jin-Fu Li, EE, NCU

23

Hierarchical Test Manager Test Manager Boundary Register Selection Register Bypass Register Instruction Decoder Instruction Register

FSM TMS TCK TRST

ECS0 ECS1 ECS2

WCS Encoder

TDI TDI

TMS_N _ TCK_N TRST_N

TMS TCK TRST

TDI_UP

Switch

TDO_UP

Box Hierarchical Test Interface Advanced Reliable Systems (ARES) Lab.

Jin-Fu Li, EE, NCU

TDI_C TDI C TDI_H TDO_C TDO H TDO_H 24

Example 1 „ A megacore is defined as a design contains nonmergeable embedded cores „ An illustration of a megacore with a predesigned TAM architecture Mega-core S Scan_data_in d t i 1

Internal scan chain

Scan_data_out1

Scan_data_in2

Internal scan chain

Scan_data_out2

{

Data in Data_in

Embedded core

Embedded core

Wrapper

Wrapper

{

Data out }Data_out

}TAM (out)

TAM1(in)

1

Embedded core

Embedded core

Wrapper

Wrapper

{

TAM2(in)

Advanced Reliable Systems (ARES) Lab.

}TAM (out) 2

Jin-Fu Li, EE, NCU

25

Example 2 „

An illustration of a two-part wrapper for the megacore that is used to drive the TAMs in the megacore and to test the logic external to the embedded cores Wrapper 1

Mega-core

Scan_data_in1

Internal scan chain

Scan_data_in2

Internal scan chain

Data_in

TAMin

Scan_data_out1

Scan_data_out2 Data_out

Embedded core

Embedded core

Wrapper

Wrapper

Mux

TAMout

TAM1(out)

TAM1(in) Embedded core

Embedded core

Wrapper

Wrapper

MUX select TAM2(out)

TAM2(in)

Wrapper 2 Advanced Reliable Systems (ARES) Lab.

Jin-Fu Li, EE, NCU

26

Network-on-Chip (NoC) „ An example of a mesh-based network-onchip p core 1

router core 5

32

router core 10

router core 3

core 2 router

core 6 router

core 9

Advanced Reliable Systems (ARES) Lab.

router core 4

router core 8

router

router

router core 7

router

Jin-Fu Li, EE, NCU

router

27

Network-on-Chip Testing „ Testing an NoC-based system includes testing g of embedded cores and testing g of the on-chip network „ Testing of embedded cores is similar to conventional SOC testing „ Testing of on-chip network „ Testing of interconnects, switches/routers input/output ports, switches/routers, ports and other mechanism other than the cores

Advanced Reliable Systems (ARES) Lab.

Jin-Fu Li, EE, NCU

28

Reuse of On-Chip Network for Testing „ Wrapper configurations of cores in NoC-based system in test mode Scan control

NOC

NOC

Core

Advanced Reliable Systems (ARES) Lab.

Jin-Fu Li, EE, NCU

29

Reuse of On-Chip Network for Testing „ Wrapper configurations of cores in NoC-based system in function mode Scan control

NOC

NOC

Core

Advanced Reliable Systems (ARES) Lab.

Jin-Fu Li, EE, NCU

30

Test Ports and Routing Paths core 1 router core 5

32

router core 10

router input

core 3

core 2 router

core 6 router

input

router

core 9

output

Advanced Reliable Systems (ARES) Lab.

core 4

router core 8

router

router

router output

router

Jin-Fu Li, EE, NCU

core 7 router

31

Test Access Methods „ An example of testing of identical cores using IEEE 1149.1 Boundary scan registers

NODE

TAP

NODE

NODE

NODE

NODE

NODE

TAP TAP

comparator p

Advanced Reliable Systems (ARES) Lab.

Jin-Fu Li, EE, NCU

32

Test Interface „ To reuse the network to transport test data, a test interface has to be established to handle both functional protocol from network and test application to the core „ A wrapper is needed for each core as an interface „ Left figure shows a standard IEEE1500 wrapper cell „ Right figure shows a modified wrapper cell for NoC testing shift

nomal_mode

shift

nomal_mode prot_mode

prot_in func_in scan in scan_in

clock Advanced Reliable Systems (ARES) Lab.

func out func_out scan_out

func_in scan in scan_in

clock

Jin-Fu Li, EE, NCU

func_out

scan_out

33

Efficient Reuse of Network „ One challenge in this reuse-based approach is that the channel width is determined by the system performance f in i d design i process and dh hence cannot be optimized for test purpose „ In the context conte t of net network o k reuse e se in NoC test, test the available TAM or channel width for wrapper scan chain design is already determined by the bandwidth requirements of cores in mission mode, not for test mode „ For example, if the channel width is predesigned to be 4, then half of the channel wires will be idle during core test while the core under test only has two scan chains Advanced Reliable Systems (ARES) Lab.

Jin-Fu Li, EE, NCU

34

Wrapper Scan Chains „ Core test wrapper is usually designed through the use of balanced wrapper scan chains „ Left figure is an example of unwrapped core „ Right figure is an example of balanced wrapper scan chain design Primary outputs

Primary inputs

Core Core

Core

Wrapper scan chains

4 FF

4 FF

8 FF

8 FF Advanced Reliable Systems (ARES) Lab.

Test wrapper pp

Jin-Fu Li, EE, NCU

35

Utilization of the Reused Channel „ Time-multiplexing technique can be used to increase the utilization of test channel „ E.g., test architecture using on-chip clocking Fast on-chip clock

Slow tester clock

Core B tested using on-chip clock

PLL

T t Tester

Mux Test data

Wrapper Wrapper Core A

Core A tested using slow clock

SoC Advanced Reliable Systems (ARES) Lab.

Router

4

Router 4

Core B

Network channel Jin-Fu Li, EE, NCU

36

Reconfigurable Data Flit Format „ Another technique can be used to increase the utilization of the reused channel „ Reconfigurable data flit „ Example: Data flit 8 bits

Embedded core 160FF

8 bits

160FF

8 bits

80FF

8 bits

Data flit

80FF

Advanced Reliable Systems (ARES) Lab.

Embedded core 160FF

16 bits

160FF 80FF 16 bits bit

80FF

Jin-Fu Li, EE, NCU

37

Testing of On-Chip Networks „ Testing of on-chip networks „ Testing of interconnects and routers „ Testing of interconnects „ Maximal aggressor fault (MAF) model is typically used for testing of on-chip interconnects „ An example of BIST for interconnect testing

Advanced Reliable Systems (ARES) Lab.

switch

TEG

switch

TDG

Jin-Fu Li, EE, NCU

38

Interleaved Unicast MAF Test

TED

TED

TDG GTC

Jin-Fu Li, EE, NCU

TED

TED

TED

TED

Advanced Reliable Systems (ARES) Lab.

TED

39

Interleaved Multicast MAF Test TED

TED

TDG GTC

Jin-Fu Li, EE, NCU

TED

TED

TED

TED

Advanced Reliable Systems (ARES) Lab.

TED

40

Routers „ A typical organization of a router IOs of the NoC and the Router Local port

IP FIFO

OP

IP FIFO OP

FIFO

Switch

IP

OP

FIFO

IP

Advanced Reliable Systems (ARES) Lab.

OP

routing/ arbitration

Jin-Fu Li, EE, NCU

output port

Primary outputs of the Router

Primary inp puts of th he Router

input port

41

Testing of Routers „ Router testing has been dealt with in three parts „ The testing of each router „ The testing of all routers (without considering network interfaces and interconnects) „ The testing of wrapper design

„ Testing a router „ Testing g the control logic g ((routing, g, arbitration,, and flow control modules) „ Testing the FIFOs „ Testing T ti th the control t l logic l i can be b done d using i traditional t diti l sequential circuit testing methods „ One approach pp to test FIFO „ Configure the first register of the FIFO as part of a scan chain, and other registers can be tested through this scan chain Advanced Reliable Systems (ARES) Lab.

Jin-Fu Li, EE, NCU

42

Testing multiple identical Routers „ The FIFOs in a router is configured as a scan chain „ Multiple routers can be tested in parallel router 0

router 1

SI0

NoC

= router 2

SO0

router 3

Se0..4

Advanced Reliable Systems (ARES) Lab.

Jin-Fu Li, EE, NCU

43

Test Wrapper Design for Routers „

An IEEE-1500 compliant test wrapper should be designed to support test pattern broadcasting and test response comparison modifications required for the test wrapper

NoC

router 0

Sc1 [0:n]

Si[0:2]

se[0..r] =

Sc0 [0:m]

=

Sc1 [0:n]

ci1

20

S [0 2] So[0:2]

=

router n

ci0

Diagnosis Control block

cO0 =

Sc0 [0:m]

cO0

[0]

Din_R0 [0:19]

. . . Din_Rn [0:19]

special_in Advanced Reliable Systems (ARES) Lab.

[0]

Dout_R0 [0:19]

Functional ports router 0 [19]

[19]

[0]

[0]

. . . Rn Dout_Rn Dout

Functional ports router n [19]

control ports

Jin-Fu Li, EE, NCU

Functional outtputs

Functio onal inpu uts

9

[0:19]

[19]

test wrapper

44

Design of Reliable On-Chip Networks [Source: pp pp. 655-667, 655-667 June June, 2005 2005, TVLSI]

„ Generic communication system

„ Generic coding system for an on on-chip chip bus

Advanced Reliable Systems (ARES) Lab.

Jin-Fu Li, EE, NCU

45

Design of Reliable On-Chip Networks [Source: pp pp. 655-667, 655-667 June June, 2005 2005, TVLSI]

„ An unified coding framework for on-chip networks

Advanced Reliable Systems (ARES) Lab.

Jin-Fu Li, EE, NCU

46

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Network-on- Chip Test Architectures

Chapter p 5 System/Network--on System/Network on-Chip Test Architectures Jin-Fu Li Advanced Reliable Systems (ARES) Lab Department of Electrical Engin...

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