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System-on-Chip Test Architectures Nanometer Design for Testability A volume in Systems on Silicon Edited by:Laung-Terng Wang, Charles E. Stroud and Nur A. Touba ISBN: 978-0-12-373973-5

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Preface, In the Classroom, Acknowledgments, Contributors, About the Editors



Chapter 1 - Introduction , Pages 1-40, Laung-Terng (L.-T.) Wang, Charles E. Stroud, Nur A. Touba



Abstract

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Chapter 2 - Digital Test Architectures, Pages 41-121, Laung-Terng (L.-T.) Wang Abstract

This book is a comprehensive guide to new VLSI Testing and Design-for-Testability techniques that will allow students, researchers, DFT practitioners, and VLSI designers to master quickly System-on-Chip Test architectures, for test debug and diagnosis of digital, memory, and analog/mixed-signal designs. Emphasizes VLSI Test principles and Design for Testability architectures, with numerous illustrations/examples. Most up-to-date coverage available, including Fault Tolerance, Low-Power Testing, Defect and Error Tolerance, Network-on-Chip (NOC) Testing, Software-Based Self-Testing, FPGA Testing, MEMS Testing, and System-In-Package (SIP) Testing, which are not yet available in any testing book. Covers the entire spectrum of VLSI testing and DFT architectures, from digital and analog, to memory circuits, and fault diagnosis and selfrepair from digital to memory circuits. Discusses future nanotechnology test trends and challenges facing the nanometer design era; promising nanotechnology test techniques, including Quantum-Dots, Cellular Automata, Carbon-Nanotubes, and Hybrid Semiconductor/Nanowire/Molecular Computing. Practical problems at the end of each chapter for students.



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Chapter 3 - Fault-Tolerant Design , Pages 123-170, Nur A. Touba Abstract

Modern electronics testing has a legacy of more than 40 years. The introduction of new technologies, especially nanometer technologies with 90nm or smaller geometry, has allowed the semiconductor industry to keep pace with the increased performance-capacity demands from consumers. As a result, semiconductor test costs have been growing steadily and typically amount to 40% of today's overall product cost.

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Table of Contents



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Chapter 4 - System/Network-On-Chip Test Architectures, Pages 171-224, Chunsheng Liu, Krishnendu Chakrabarty, Wen-



Ben Jone Abstract

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Chapter 5 - SIP Test Architectures, Pages 225-261, Philippe Cauvet, Michel Renovell, Serge Bernard Abstract



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Chapter 6 - Delay Testing, Pages 263-306, Duncan M. (Hank) Walker, Michael S. Hsiao Abstract



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Chapter 7 - Low-Power Testing, Pages 307-350, Patrick Girard, Xiaoqing Wen, Nur A. Touba Abstract



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Chapter 8 - Coping with Physical Failures, Soft Errors, and Reliability Issues, Pages 351-422, Laung-Terng (L.-T.) Wang,



Mehrdad Nourani, T.M. Mak Purchase PDF - $31.50 Abstract

Chapter 9 - Design for Manufacturability and Yield , Pages 423-461, Robert C. Aitken Abstract



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CHAPTER 10 - Design for Debug and Diagnosis, Pages 463-504, T.M. Mak, Srikanth Venkataraman Abstract



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CHAPTER 11 - Software-Based Self-Testing, Pages 505-548, Jiun-Lang Huang, Kwang-Ting (Tim) Abstract



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Chapter 12 - Field Programmable Gate Array Testing, Pages 549-590, Charles E. Stroud Abstract



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Chapter 13 - MEMS Testing, Pages 591-651, Ramesh Ramadoss, Robert Dean, Xingguo Xiong Abstract



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Chapter 14 - High-Speed I/O Interfaces, Pages 653-701, Mike Peng Li, T.M. Mak, Kwang-Ting (Tim) Cheng Abstract



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Chapter 15 - Analog and Mixed-Signal Test Architectures, Pages 703-743, F. Foster Dai, Charles E. Stroud Abstract

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Chapter 16 - RF Testing, Pages 745-789, Soumendu Bhattacharya, Abhijit Chatterjee Abstract



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Chapter 17 - Testing Aspects of Nanotechnology Trends, Pages 791-831, Mehdi B. Tahoori, Niraj K. Jha, R. Iris Bahar Abstract



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Index, Pages 833-856 First page PDF





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